1. Field of the Invention
The present invention is directed to trenching techniques for forming channels and vias in substrates, and more particularly to methods for fabricating channels and vias in the insulating layer of a substrate, and using the channels as conductive lines, electrodes of integrated capacitors, and/or optical waveguides.
2. Description of the Related Art
High density copper/polyimide interconnect substrates can be fabricated by providing conductors on a base, building interlayer pillars on the conductors, and coating the conductor-pillar structure with polyimide. This has several drawbacks: the metal conductor-pillar structure is vulnerable to mechanical damage before polyimide encapsulation; resist scumming can develop on underlying patterned layers after wet chemical etching; particles on the surface prior to plating can plate up quickly causing interlayer short circuits; and cooling after the 400.degree. C. polyimide cure can create stress between the copper and polyimide since copper has a different thermal coefficient of expansion.
These drawbacks associated with conductor-pillar structures can be overcome by forming trenches for vias and channels in a polyimide layer and then filling the trenches with a conductor. One such method for fabricating high density electronic circuits having narrow conductors is disclosed by Becker in U.S. Pat. No. 4,417,393. However, drawbacks to Becker's method include the need for laser machining and the inability to incorporate electrodeposition.
Furthermore, current interconnect fabrication methods with relatively few steps form conductive channels and vias simultaneously but fail to provide via stacking. Alternative methods which provide via stacking require a relatively large number of process steps.